The memory cells of dynamic random access memories are comprised of two main components: a field-effect transistor and a capacitor. In DRAM cells utilizing a conventional planar capacitor, far more chip surface area is dedicated to the planar capacitor than to the field-effect transistor (FET). Wordlines are generally etched from a doped polysilicon layer. A doped region of silicon substrate functions as the lower (storage-node) capacitor plate, while another doped polysilicon layer generally functions as the upper capacitor plate (cell plate). As component density in planar DRAM chips increased, the shrinkage of cell capacitor size resulted in unacceptably high soft-error rates, lower differential signal strength at column sense amplifiers, and shortened cell refresh times. Although planar capacitors have generally proven adequate for use in DRAM chips up to the one-megabit level, they are considered to be unusable for more advanced DRAM generations.
As a result of the problems associated with the use of planar capacitors for high-density DRAM memories, all manufacturers of 4-megabit DRAMs are utilizing cell designs based on non-planar capacitors. Two basic non-planar capacitor designs are currently in use: the trench capacitor, and the stacked capacitor. Both types of non-planar capacitors typically require a considerably greater number of masking, deposition and etching steps for their manufacture than does a planar capacitor.
In a trench capacitor, charge is stored primarily vertically, as opposed to horizontally in a planar capacitor. Since trench capacitors are fabricated in trenches which are etched in the substrate, the typical trench capacitor, like the planar capacitor, is subject to soft errors. In addition, there are several other problems inherent in the trench design. One problem is that of trench-to-trench charge leakage, caused by the parasitic transistor effect between adjacent trenches. Another problem is the difficulty of completely cleaning the trenches during the fabrication process; failure to completely clean a trench will generally result in a defective cell.
Most manufacturers of 4-megabit DRAMS are utilizing stacked capacitor designs. Since both the lower and the upper plates of a typical stacked capacitor are formed from individual conductive layers, the stacked capacitor is generally much less susceptible to soft errors than substrate-based planar and trench designs. By placing the wordline and, in some designs, also the digitline beneath the capacitive layers, and having the lower layer make contact with the substrate by means of a buried contact, some manufacturers have created stacked capacitor designs in which vertical portions of the capacitor contribute significantly to the total charge storing capacity. Since a stacked capacitor generally covers not only the entire area of a cell (including the cell's access FET), but adjacent field oxide regions as well, capacitance is considerably enhanced over that available from a planar type cell.
The electrodes, or plates, of a stacked capacitor are typically patterned from individual layers of conductively-doped polycrystalline silicon (hereinafter also "polysilicon"). There are a number of peculiarities and problems inherent with the use of polysilicon capacitor plates.
Conductively-doped polysilicon layers are generally created by depositing a layer of undoped polysilicon via chemical vapor deposition (CVD), and then doping the deposited layer. The doping step is typically performed by placing a substrate, on which the undoped polysilicon layer has been deposited, in a reactor chamber, introducing phosphine or phosphorus oxychloride and oxygen gases into the chamber at a temperature sufficient to cause the formation of a P.sub.2 O.sub.5 and SiO.sub.2 glaze layer on the polysilicon surface. When the thickness of the glaze layer has reached 200-500.ANG., the phosphine or phosphorus oxychloride and oxygen gases are shut off, the temperature of the reactor chamber is either maintained or increased, and nitrogen gas is introduced into the chamber. This condition is maintained until the desired amount of phosphorus has diffused from the glaze layer into the polysilicon layer. One of the problems with this method of doping is that the undoped polysilicon layer must be thicker than the thickness desired for the DRAM capacitor plates, as some polysilicon is consumed during the in situ doping process. A thickness of 600.ANG. is considered a realistic minimum value for initial undoped layers. As cell geometries are shrunk, thicknesses of such magnitude may pose a problem for doping vertically-oriented portions of the layer which occur, for example, in interwordline gap regions. The steps required for doped polysilicon layer formation also represent a manufacturing cost.
Another problem related to the use of a conductively-doped polysilicon layer for the bottom plate of a DRAM capacitor is that the dopant impurities from the polysilicon layer tend to diffuse into the channel of the cell access transistor. This problem becomes more acute as cell geometries are shrunk, resulting in shorter channel lengths and thinner gate sidewall spacers.
Yet another disadvantage related to the use of conductively-doped polysilicon layers for DRAM capacitor plates is the fact that the native oxide (SiO.sub.2) must be utilized as at least a component of the cell dielectric layer. Most contemporary DRAM cells use an oxide-nitride-oxide (ONO) dielectric layer. The problem with SiO.sub.2 is that it has a relatively low dielectric constant, which negatively impacts cell capacitance. In addition, direct tunneling current greatly increases below an effective SiO.sub.2 film thickness of 4 nm. In order to further miniaturize DRAM memories, it will be necessary to decrease the operating voltage from 3.3 V to 1.5 V. Since Q=CV, where Q is the stored charge, C is the capacitance, and V is the voltage, if the voltage is lowered, the capacitance must be raised to maintain a constant charge.
Tantalum pentoxide, on account of its relatively high dielectric constant, has received considerable attention as a potential replacement for the ONO dielectric layers that are currently the norm for contemporary DRAM's. Since the dielectric constant of tantalum pentoxide is approximately 20 (vs. 8 for a typical ONO dielectric), greater charge may be stored within a cell capacitor for a given dielectric thickness. Until recently, however, the high leakage currents normally associated with tantalum pentoxide films have precluded their use as DRAM cell dielectrics. Hitachi Corp. has developed a new two-step process for annealing tantalum pentoxide films deposited via low-pressure chemical vapor deposition so as to reduce leakage current to levels that are compatible with DRAM cell dielectrics. The first step, called UV-O.sub.3 annealing, involves subjecting the tantalum pentoxide film to an ozone (9-percent by volume)/oxygen mixture irradiated by ultraviolet light provided by a mercury lamp. The second step is performed at 800.degree. C. in a dry oxygen ambient and is called dry-O.sub.z annealing.
What is needed is a DRAM cell which eliminates the problems associated with polysilicon lower capacitor plates, and which combines a tantalum pentoxide cell dielectric layer for increased cell capacitance.